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PROLITH™: Virtual Patterning Solution

Mar 4, 2021 5 min read

PROLITH™ 2020b and PROLITH™ Enterprise 2020b

PROLITH™ 2020b is the latest version of our virtual lithography and patterning system. PROLITH 2020b supports all lithography technologies – from g-line to EUV – with emphasis on EUV, immersion ArF, spacer-based SADP and thick resist lithography for 3D interconnects and MEMS, LED and 3D IC manufacturing.

PROLITH™ Enterprise 2020b combines all the core features of PROLITH 2020b with the ability to distribute large simulation jobs. This capability is critical to supporting in-fab simulations necessary for troubleshooting patterning issues related to state-of-the-art immersion ArF or EUV lithography processes. PROLITH Enterprise also offers a new, enhanced dissolution model that accurately describes the behavior of Negative Tone Development (NTD) chemically amplified resists used in EUV lithography. The new NTD stochastic model in PROLITH Enterprise 2020b helps teams simulate and characterize CD distribution and isolate stochastic weak spots before they become potential device failure mechanisms. 

Accurate pattern formation is critical to successful semiconductor chip production, and lithography and patterning advancements are often the cornerstones of chip manufacturers’ technology milestones. PROLITH serves a critical role in the lithographer’s toolbox, helping to drive faster product development.

PROLITH simulation capabilities

Stochastic Modeling
Stochastic Modeling for EUV and ArF CDU and LER
Topography Modeling
Topography Capabilities for FinFET, SAxP and Damascene Modeling
Simulation of Multiple Patterning

Simulation of Multiple Patterning (LELE and SAxP)
Thick Resist Modeling
Thick Resist Modeling and Advanced Metrology for MEMS/LED and 3D IC

Continue reading to learn more about the history and technology of lithography.

Lithography Fundamentals

Semiconductor chips are fabricated by adding and subtracting layer after layer of materials in carefully planned patterns, forming a nanoscale network of wires and transistors that power our everyday electronics. Within a semiconductor fab, lithography processes are the manufacturing steps where the precise patterns are created. Lithography utilizes light and optics to transfer a geometric pattern from a reticle to a chemically active material (called a resist) on a semiconductor wafer. This pattern transfer is accomplished in a scanner and is referred to as the exposure step. The pattern on the wafer determines where materials are subtracted and added, and multiple lithography exposure steps are used along the way to producing the final chip.

Lithography is a complex process – the pattern ultimately printed on the wafer is affected by multiple variables, including reticle design, scanner settings, wafer topography, resist composition, etc. To evaluate and fine tune all these variables, a lithographer could print test wafers. This option is time intensive and expensive as it uses scanner tool time, materials and metrology resources. A faster, more cost-effective means of investigating and optimizing advanced lithography processes involves simulating patterning results – a technique referred to as computational lithography. By computing patterning results using different variable settings, lithography researchers can quickly determine optimal lithography settings, without the expense of processing actual wafers.

Pattern Transfer
During lithography exposure steps, pattern is transferred from a reticle to resist material on a wafer.

Technological Evolution

Computational lithography began in the early 1970s at IBM Yorktown Heights, with the goal of translating the steps of this artful “litho” process into practical, physics-based mathematical equations.1 Back then, the patterning process was much more straightforward. The lithography tool printed the pattern and all chips onto the entire wafer using a single exposure of broadband light, producing semiconductor devices with a minimum transistor feature size in the 5 to 10µm range. 

Over the years, to increase chip performance (increased speed, lower power consumption, smaller footprint), the patterns printed during manufacturing have shrunk. To pattern these smaller chips with more densely packed patterns, lithography equipment achieved finer resolution by implementing shorter wavelengths of light, and printing a die, or a cluster of die with individual alignment and exposures using projection steppers and scanners. More recent lithography revolutions include immersion and Extreme Ultraviolet (EUV) scanners, self-aligned double and quadruple patterning (SADP, SAQP) processes, and several computational techniques including reticle optical proximity correction (OPC), inverse lithography technology (ILT), source-mask optimization (SMO), design technology co-optimization (DTCO), and lithography process simulation. These incredible engineering solutions have made it possible to print much smaller, more complex features on a wafer and produce the most powerful chips in today’s everyday electronic devices. 

Semiconductor Device Scaling and Lithography Technology

Today’s Challenges

However, today’s advanced lithography is not without its challenges. At the very short wavelengths used in EUV lithography (13.5nm), the energy from the light source is distributed over drastically fewer photons, resulting in greater variability and a decreased signal-to-noise ratio in the printed image.2 The resulting fluctuations in the projected image at the wafer surface create localized “stochastic” printing failures that are random in nature, non-repeating and difficult to locate.3,4 Stochastic defects may be micro-bridges, tiny opens, shortening of features, or missing or merged contacts – all detrimental to chip functionality. Even more subtle issues include pattern roughness – line edge roughness (LER) and linewidth roughness (LWR) – and edge placement error (EPE). Stochastic defects may print in some exposure fields but not in others (also known as “soft” repeaters), making prediction and experimental detection even more challenging. To combat this, computational lithography has evolved to include stochastic modelling in order to help fabs using EUV predict where defects are most likely to appear and how frequently they will impact yield.

KLA’s Solutions

Our PROLITH™ lithography and patterning simulation solution is used by IC, LED and MEMS fabricators; scanner, track and mask manufacturers; material suppliers; and research consortia to cost-effectively evaluate various patterning technologies in R&D. University students also use PROLITH to gain an understanding of lithography, optics, resist chemistry and the semiconductor fabrication process. PROLITH uses calibrated, physics-based models to accurately simulate how various types of lithography, including EUV and multiple patterning process techniques, will print on the wafer – eliminating the need to manufacture reticles or print hundreds of test wafers experimentally. To evaluate process robustness, PROLITH helps lithographers simulate and characterize the impact of multiple lithography variables, such as scanner illumination, exposure dose, focus, wafer topography and more, while significantly reducing the time required to identify solutions. PROLITH data allow users to adjust and re-optimize additional variables between modeling iterations, such as mask OPC, scanner source shape, dose, focus, resist thickness, developer processing and more, to achieve the desired results. 

  1. F. H. Dill, A. R. Neureuther, J. A. Tuttle and E. J. Walker, “Modeling projection printing of positive photoresists,” in IEEE Transactions on Electron Devices, vol. 22, no. 7, pp. 456-464, July 1975, doi: 10.1109/T-ED.1975.18161
  2. Katherine Derbyshire, “Finding The Source Of EUV Stochastic Effects: Semiconductor Engineering, April 15, 2019
  3. Pete Singer, “EUV Lithography: Sailing Along the Stochastic Cliffs”, Semiconductor Digest, Feb. 4, 2020
  4. K. Sah, S. Halder, A. Cross and P. Leray, “Inspection of Stochastic Defects With Broadband Plasma Optical Systems for Extreme Ultraviolet (EUV) Lithography,” in IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 1, pp. 23-31, Feb. 2020, doi: 10.1109/TSM.2019.2963483.

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