Today’s chip manufacturers contend with strict requirements when it comes to quality assurance, since more complex chips are powering increasingly sophisticated, higher-performing and more expensive high-tech devices. The reliability and integrity of these devices – calling cards for their respective OEM brands – hinges on the integrity of each individual chip within them, from single-die packages to more complex, integrated multi-chip packages.
“Chip manufacturers can answer these challenges with advanced process control technologies, and KLA’s innovations and investments in ‘zero tolerance’ defect inspection are helping set the bar for continued gains in chip integrity, manufacturing throughput and yield. By reducing the material losses associated with defective chips, chip manufacturers can also make better use of limited material supplies while reducing waste, over the long term.”
Pieter Vandewalle, general manager, ICOS division, KLA
Overkill and Underkill Optimization
Zero tolerance means more than just ensuring that defective chips don’t negatively impact customers’ product lines. Chip manufacturers must also grapple with instances where good chips are incorrectly deemed faulty and removed from production (overkill), or the alternative where a killer defect is missed, and the chip is allowed to move onto the next manufacturing step (underkill). For both cases, the associated cost penalties and material waste can mount quickly. To achieve a careful, consistent, cost-effective balance between overkill and underkill – without compromising high-speed throughput – chip manufacturers look for the latest innovations in die sorting and inspection.
KLA’s new ICOS™ F260 system addresses this trend, delivering inspection and workflow enhancements on a platform that’s been redesigned from the ground up to deliver industry-leading accuracy and greater overall throughput to support high-volume manufacturing. The ICOS F260 offers the fully automated ability to detect both internal and superficial chip defects with extremely low overkill and underkill rates to help optimize yield.
Unique Inspection Capabilities
The ICOS F260 is designed for the sorting and inspection of diced bare die and advanced wafer-level packages (WLP) at high speeds up to 40,000 units per hour (UPH). The new systems are optimized to detect hairline (sub-micron) sidewall cracks and chipped die edges caused during mechanical saw blade dicing and hybrid mechanical-laser dicing – and it achieves this with the highest accuracy available in the industry today.
These hairline defects are often so small that they can’t be effectively detected using electrical testing techniques. Instead, chip manufacturers turn to automated die sorting and inspection systems like the ICOS™ F260 for high-speed detection of these yield-limiting issues.
The ICOS F260 is unique in its ability to use short wave infrared (IR) light at high throughput speeds for sidewall and laser groove area inspection. Because silicon is transparent to short wave IR, more photons can pass through the device, being captured and processed by a sensor on the opposite side to deliver precise, edge-to-edge defect detection. Systems using near-infrared (NIR) wavelengths offer a limited, superficial depth of vision into the device since transmissions are largely absorbed into the silicon.
The ICOS F260’s enhanced laser groove crack (LGC) inspection capability using short wave IR combined with a customized optical path offers more accurate visualization of narrow chip edges prone to heat-related cracks and defects resulting from laser grooving processes. Finally, using specialized cameras, operating in the visual wavelength, to inspect the top and bottom sides of the device, the ICOS F260 gives operators a complete six-sided view of the die with unrivaled resolution and precision.
Improved Workflow Versatility
In addition to the boost in throughput, the ICOS F260 die sorting and inspection systems improve total cost of ownership in other ways, supporting a variety of input and output mediums spanning wafer, tape and chip tray. Changeover times to accommodate different die geometries are reduced to an hour or less, and these supported device geometries can range from 0.5×0.5 mm to 10×10 mm (12×12 mm optional) configurations or custom form factors.
For high-precision defect detection and high-speed throughput, KLA’s ICOS die sorting and inspection systems set a new benchmark for chip manufacturers seeking to optimize yield and minimize material waste. Moreover, the ICOS F260 system gives chip manufacturers – and their customers – the confidence that chip defects won’t go undetected and manifest later as expensive device recalls (and brand blemishes). Electronic device OEMs can maintain the chip-level integrity they require as package complexity increases, with zero tradeoffs between quality inspection and speed.
Please see the die sorting and inspection page for more information on the ICOS F260 system, or visit KLA’s packaging portfolio page to learn about our portfolio of packaging process control and process-enabling solutions for wafers, packaged components and IC substrates.
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